Since early 2020, SMIC has been discussing its N+1 fabrication technique, which is generally regarded as the company’s 7nm-class node. It has been positioned as a low-cost alternative to TSMC’s N7 node, which depends on deep ultraviolet (DUV) lithography equipment. Compared to a chip made using SMIC’s 14nm process, N+1 hopes to cut power consumption by 57%, boost performance by 20%, and reduce the logic space by up to 55% to 63%. -Chen Jia (Global Times) Recent TechInsights research demonstrates that SMIC’s N+1 technology is similar to TSMC’s N10 technology, with more lenient restrictions and robust Design Technology Co-Optimization (DTCO) characteristics. Since July 2022, SMIC has been secretly manufacturing the Bitcoin mining chip used by MinerVa Semiconductor. The business manufactures such small 25W mining chips using its DUV machinery. They provide a means of learning more about the process performance, power, and defect density and are simple enough to provide acceptable yields for commercial applications. From the perspective of logic transistor density, SMIC’s N+1 might replace TSMC’s N7. However, the world’s biggest contract chip manufacturer already uses far more sophisticated manufacturing techniques attractive to designers of complicated CPUs, compute GPUs and other high-end data centre-grade circuits. As a consequence, SMIC may have trouble attracting high-profile clients for N+1. It is plausible to anticipate that the 5nm manufacturing process will be completed sometime in 2023 since SMIC has been working on its N+2 node for well over two years and businesses prefer to discuss new nodes when they have a more or less clear view of their objectives and strategies to accomplish them. It is clear from SMIC’s N+1 qualification and readiness for at least limited production that the firm can survive without the extreme ultraviolet (EUV) manufacturing equipment that it cannot acquire due to U.S. government sanctions. However, it remains to be seen if the business can manufacture substantial and intricate system-on-chips utilising its N+1 node.
